1. Field of the Invention
The present invention relates to an error control apparatus and method using a cyclic code in communication, and more particularly, to an error control apparatus and method using a communication system that may switch between communication using data interleaving and communication not using data interleaving.
2. Description of the Background Art
In recent years, communication devices using radio communication such as a portable telephone is being widespread. The radio communication does not require a telephone line or the like in an ordinary telephone system and can be performed by providing base stations in proper places. Consequently, the radio communication is most suitable to use in an area where cost of laying a telephone line seems to be excessive. Moreover, since locations where communication can be conducted are not always limited, the radio communication is expected to be more widely used in the future.
In the radio communication, digital communication is mainly used. Particularly, in the radio communication, for example, in order to protect privacy of conversation by telephone, it is preferable to use the digital communication.
In the digital communication, there is a case such that an error control system in which a coding system using an error correcting code and a CRC code are combined is used. Particularly, as seen in a part of the standards of recent portable telephone systems, at the time of transmission from a base station to a mobile station, when the state of communication is seen from the mobile station and the quality of a radio line is good, a CRC code obtained by CRC which does not perform interleaving is added to data and the resultant is transmitted. When the quality of the radio line is not good, data is coded by an error correcting code, and a CRC code obtained by the CRC performing interleaving is added to data. In such a manner, there is a case that the system of the CRC code changes according to the line quality.
Data that is not interleaved includes, like reception data 120 shown in FIG. 9, 224 bits of data D0 to D223 (208 bits of data from D0 to D207 and 16 bits of CRC bits from D208 to D223). The data bits are sequentially transmitted in accordance with the order. The data is stored into a reception buffer in this order, sequentially read in this order, and decoded for an error control by the CRC. As an example, the code length of 224 bits, 16-bit CRC, and 16-stage interleaving are assumed here.
Referring to FIG. 10, reception data 130 is interleaved not in the order of D0 to D223 but in the order of D0, D16, D32, . . . , D209, D1, D17, D33, . . . , D210, . . . , D222, D15, D31, D47, . . . , D207, D223. The interleaved reception data 130 is transmitted, read in this order as shown by arrows 132, and decoded for an error control by the CRC. Particularly, such interleaving is performed by adding an error correction signal when line quality is poor.
Data formatting with/without interleaving is done on the base station side. A mobile unit cannot know whether data received from the base station is interleaved data or not. Conventionally, the mobile unit performs error detection by a CRC circuit on the assumption that the received data is interleaved. When there is no error, it is determined that the received data is in an interleaved format and the process is continued. When there is an error, it is determined that the received data is in a format without interleaving. The mobile unit regards the data as data that is not interleaved and performs error detection again by the CRC circuit. When a CRC error is further detected in the process, a proper error process such as retransmission of data is performed. When the error correcting code is added, error correction by the error correcting code is also conducted at this time. A technique of transmitting data by adding the error correcting code is called an FEC (Forward Error Correction), and a circuit for the FEC is called an FEC circuit. Since the invention relates to a CRC decoding process and does not relate to the FEC, in order to make the description regarding the invention clear, the FEC will not be considered in the following description.
An example of a circuit for realizing the above-described CRC process is shown in FIG. 7. Referring to FIG. 7, a conventional error control decoding unit 90 includes: a reception data buffer 50 for storing data received from a base station; a deinterleaver 52 for deinterleaving data by reading data in accordance with a predetermined order on the assumption that data stored in the reception data buffer 50 is interleaved data (in an interleave format); an FEC 54 for receiving an output of the deinterleaver 52; an FEC 56 for receiving data read directly from the reception data buffer 50; a selector 100 for selecting and outputting either data of the FEC 56 or data of the FEC 54; and a CRC circuit 58 for receiving an output of the selector 100 and calculating CRC of the data.
Referring to FIG. 11, as is well known, the CRC circuit 58 includes: a plurality of 1-bit registers CR0 to CR15 that are connected in series so as to sequentially shift data (the number of the 1-bit registers is determined by a CRC generation polynomial); adders 142 and 144 each inserted in front of the 1-bit register in a position corresponding to a coefficient except for 0 in coefficients in each term in the CRC generation polynomial, for performing addition by using 2 as a modulus between data supplied via a data line 140 and an output of the immediately preceding 1-bit register and supplying the result to the immediately following 1-bit register; and an adder 146 for performing addition using 2 as a modulus between input data and an output of the last 1-bit register CR15 and supplying the result to the head 1-bit register CR0 and the adders 142 and 144 via the data line 140. FIG. 11 shows the CRC circuit corresponding to the following generation polynomial.
g(x)=x16+x22+x5+1
The CRC circuit is substantially a dividing circuit.
In the CRC circuit, a predetermined initial value is set in each of the 1-bit registers in the beginning, reception data is supplied as input data bit by bit, and the value is sequentially shifted by the 1-bit registers. When all of bits are inputted, the values held in the 1-bit registers CR0 to CR15 are a reminder of division, that is, CRC bits. Usually, when the CRC bit is 0, it is determined that there is no error. When the CRC bit is not 0, it is determined that an error occurs.
The error detection using the circuit is performed by processes shown in the flowchart of FIG. 12. Specifically, a mobile unit is started to receive a unit (step S2). Assuming first that the reception data are interleaved, data deinterleaved via the deinterleaver 52 shown in FIG. 7 is selected by the selector 100 and is subjected to the CRC process in the CRC circuit 58 (step S30). As a result, if there is no CRC error, the control advances to step 8 and if there is a CRC error, the control advances to step S34 (determination in step S32).
When there is no CRC error, it means that data transmitted from the base station is interleaved. Consequently, a receiving process is performed on the condition that the data is interleaved. Specifically, first, in step S8, whether the unit received in step S2 is the head unit or not is determined. When it is not the head unit, the unit is discarded in step S14, and the control returns to step S2.
When it is determined in step S8 that the unit received in step S2 is a head unit, in step S10, it is determined that the data is interleaved one, a following unit is received, and the CRC process is performed on the following unit. That is, in the subsequent processes, the selector 100 selects an output of the FEC 54. Subsequently, in step S12, whether there is a following unit or not is determined. If YES, the control returns to step S10 and the process of receiving the following unit is continued. When it is determined in step S12 that there is no following unit, the control returns to step S2.
On the other hand, when it is determined in step S32 that there is a CRC error, it is determined that the data is not interleaved. In step S34, therefore, on the assumption that the data is not interleaved, the CRC process is performed. In the example shown in FIG. 7, the data is read again from the reception data buffer 50. The data sent via the FEC 56 is selected this time by the selector 100 and is supplied to the CRC circuit 58. Whether there is a CRC error or not as a result of the CRC process by the CRC circuit 58 is determined in step S36.When there is no CRC error, it is determined that the data received in step S2 is non-interleaved data, and the control moves to step S18. When there is a CRC error, without doing anything (that is, the reception unit is discarded), the control returns to step S2.
Since processes in steps S18 to S24 performed when it is determined that there is no CRC error in step S36 are similar to those in steps S8 to 14, respectively, the detailed description will not be repeated here. Step S20 is different from step S10 in that the CRC process is performed on the assumption that the reception data is non-interleaved data.
FIG. 8 shows another conventional error control decoding unit 110 for performing processes similar to those of the conventional error control decoding unit 90 shown in FIG. 7. In the example as well, first, it is assumed that reception data is interleaved, data read from the reception data buffer 50 and deinterleaved by the deinterleaver 52 is passed via the FEC 54 to a CRC circuit 58A and is subjected to a CRC process. When there is a CRC error as a result, it is determined that the data is no-interleaved data. Data is newly read from the reception data buffer 50 and, at this time, data that is not deinterleaved is sent via the FEC 56 to a CRC circuit 58B separate from the CRC circuit 58A and is subjected to the CRC process. In the example shown in FIG. 7, the single CRC circuit 58 is obtained by combining the two CRC circuits 58A and 58B shown in FIG. 8.
However, whether the data received as described above is interleaved or not cannot be determined without performing the CRC process once. First, on the assumption that the data is interleaved one, the read data is always deinterleaved and processed. When the data is actually non-interleaved one, the data has to be newly read, directly from the reception data buffer and has to be CRC processed. As a result, there is a case that data has to be read twice from the reception data buffer, and processing time corresponding to the process of twice is required. The CRC calculation is executed twice. Consequently, the system load on the mobile unit increases, and there is a problem such that the power consumption of the mobile unit increases. Since the power of the mobile unit is limited, it is preferable to suppress the power consumption as much as possible.
It is therefore an object of the present invention to provide an error control circuit and method which can reduce power consumption in an error control apparatus and method for conducting a cyclic code check on data which is whether interleaved one or not is not known in advance.
Another object of the present invention is to provide an error control circuit and method capable of determining whether data is interleaved one or not by reading data only once from a reception data buffer.
Further another object of the present invention is to provide an error control circuit and method capable of determining whether data is interleaved one or not at high speed by reading data only once from a reception data buffer.
An error control circuit according to the present invention includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes and to be interleaved in accordance with a predetermined interleave order; a first cyclic code checking circuit for receiving an output of the deinterleaver and conducting a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and conducting a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.
Simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time, the cyclic code check is conducted by the second cyclic code checking circuit while canceling an interleave effect by the deinterleaver. Consequently, when data before being subjected to deinterleave is interleaved data, the CRC is conducted by the first cyclic code checking circuit. When data before being subjected to deinterleave is non-interleave data, the CRC is conducted by the second cyclic code checking unit. Since the two kinds of cyclic code checks can be made by reading data only once at the time of deinterleave, the time required for the cyclic code check is shortened, and the load for calculation is also reduced. As a result, the power consumption of the error control apparatus is reduced.
Preferably, the second cyclic code checking circuit includes: an input data line connected to an output of the deinterleaver; a data bus including data signal lines of the number corresponding to the maximum degree of a polynomial of generating the cyclic code; a plurality of partial check bit calculating circuits each connected to the input data line and the data signal line, which are provided in correspondence with the maximum degree of a polynomial of generating the cyclic code, for calculating a check bit in a predetermined position of the cyclic code by executing a predetermined computation sequence determined by the coding system of the cyclic code and a system of the interleave on data supplied from the input data line and data on the data signal line; and a computation control unit connected to each of the plurality of partial check bit calculating circuits, for controlling the computation sequence to be performed by the partial check bit calculating circuits.
More preferably, each of the plurality of partial check bit calculating circuits includes: a computating unit connected to the computation control unit, the input data line, and the data bus, for executing a computation determined by a computation instruction signal supplied from the computation control unit on data on the input data line and data on a predetermined data line on the data bus; a data register having an input connected to an output of the computating unit and an output connected to a predetermined data line on the data bus, for holding data outputted from the computating unit and outputting the data onto the predetermined data line; and a computation result register connected to an output of the data resistor, for executing a computation using 2 as a modulus between data held by itself and an output of the data register each time computations of the number corresponding to a number obtained by dividing the predetermined number of bits by the number of stages of the interleave are finished.
An error control method according to another aspect of the invention includes: a step of deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes and to be interleaved in accordance with a predetermined interleaving order; a step of receiving data deinterleaved in the deinterleaving step, and conducting a first cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a step of receiving the deinterleaved data and conducting a second cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the step of conducting the first cyclic code check in substantially the same time.
Simultaneously with the first cyclic code check on the deinterleaved data in substantially the same time, the second cyclic code check is conducted while canceling an interleave effect by the deinterleaver. Consequently, when data before being subjected to deinterleave is interleaved data, the CRC is conducted by the first cyclic code check. When data before being subjected to deinterleave is non-interleave data, the CRC is conducted by the second cyclic code check. Since the two kinds of cyclic code checks can be made by reading data only once at the time of deinterleave, the time required for the cyclic code check is shortened, and the load for calculation is also reduced. As a result, the power consumption of the error control apparatus is reduced.
More preferably, the step for conducting the second cyclic code check includes: a step of initializing a plurality of temporary cyclic check data registers of the number corresponding to the maximum degree of a polynomial of generating the cyclic code; and a step of calculating a check bit in each of positions of the cyclic codes by performing a computation sequence made by a plurality of clock cycle computations determined by a coding system of the cyclic code and the interleave system on data deinterleaved in the deinterleaving step while using the plurality of temporary cyclic check data registers.